User:Autisticfroggy/Atmospheric Computing

There comes a point in your atmospherics career where the question "why" loses all of its meaning and only the question of "if" remains. This is that point. This is the attempt to create a formal ISA specification for a Turing complete general purposes programmable atmospheric computer that is capable of basic arithmetic and can store large amounts of memory. It has no utility aside from practice and has no implementable segments in an actual round of ss13 aside from branch logic integrated into SM setups. Do not expect proper formatting, this isn't a proper wiki guide, these are only research notes.

Atmospheric Computing Instruction Set Architecture Specification v0.3.1 (Name still pending)

Note: This is a draft document laying out the design specifications for my latest atmos autism project. I am writing this to make sure I don't forget anything and to lock in some of the stuff so that it doesn't die due to feature creep.

What is this?

The Atmospheric Computer Project is an exploratory field of atmos that aims to create a working automaton that is capable of performing basic arithmetic and logical operations, is programmable and is generally Turing complete. This document describes the specifications for the Instruction Set Architecture as well as design details and implementation details for building an atmos processor. Engineers wishing to implement this ISA are free to design their own functional units provided that it conforms to the requirements of the ISA, but for those wishing to get started with a basic computer, a memory addressing system, a clock generator and an instruction decoder are provided, as well as a general compute pipeline.

How it works:

The CAC ISA is a CISC instruction set featuring variable length sentences comprised of smaller micro-instructions with GNS-specified arguments to form a single macro instruction. The processor is programmed via a punchcard style array of gas canisters with different gas types serving as the effective "bytecode" of the instructions. A standard compute cycle works as follows:

1. The instruction counter, initially set to 000, fetches the address on the instruction tape that is equal to the current instruction count.
2. The instruction is read from the instruction tape and sent to the instruction decoder.
3. The instruction decoder reads the first word of the instruction sentence and uses it to route the rest of the sentence into the corresponding functional unit.
4. The functional unit takes in the arguments and performs the necessary reads to fetch data from memory.
5. The fetched data is sent into the compute segment of the 1 functional unit and is computed.
6. The output is written back into the functional unit's router and is sent to whichever memory unit is specified in the instruction's output argument.
7. Once the write operation is passed from the functional unit to the memory output, a signal is sent to the instruction counter.
8. The instruction counter increments by 1, or depending on the signal recieved such as in a JUMP instruction, sets the instruction counter to the appropriate instruction address.
9. A full flush of the AND gates is performed using the dilithium purge valves for one clock cycle.
10. The clock generator resets and sends a signal to the instruction counter to fetch a new instruction based on the address, going back to step 1.

Gas Numbering System (GNS)

The GNS is how data is interpreted when dealing with gases. They form the way that bytecode is read, registers/memory is addressed and generally allows you to read raw gasmixes.

• 0 - Oxygen
• 1 - Nitrogen
• 2 - Pluoxium
• 3 - Stimulum
• 4 - Water Vapor
• 5 - Carbon Dioxide
• 6 - BZ
• 7 - Nitryl
• 8 - Plasma
• 9 - Tritium

Universal Gas Variables:

• Memory - Nitrogen
• Clock - Water Vapor
• Purge - Dilithium

If you find that these gases are in use in your functional unit implementation, simply use a type transposer.

Instruction Architecture

Each instruction is a variable length sentence with a maximum length of 4 words. The first word is decoded using a fixed function decoder which then sends the up to 3 remaining words into the respective functional unit.

Notes: -Each instruction increments the instruction counter by 1 unless noted otherwise.

Instructions:

• O2 - Load
• Nitrogen - Store
• Pluoxium - Copy
• Stimulum - Add
• Water Vapor - Subtract
• Carbon Dioxide - Compare
• BZ - Jump
• Nitryl - Conditional Jump

Each instruction is described below:

Load(Target Address, Destination Address)

Is a three word long instruction containing the address of the memory to be loaded and the address of the destination. The functional unit is basically just a router with type comparators and AND gates leading to bluespace pipes tagged with the destination memory address.

Store(Target Address, Destination Address)

Is a three word long instruction containing the address of the memory to be stored and the address of the destination. The functional unit is basically just a router with type comparators and AND gates leading to bluespace pipes tagged with the destination memory address.

Add(Register 1, Register 2, Register 3)

Is a 4 word long instruction that destructively reads data from Register 1 and 2 and adds them, then sends them to a functional unit for addition and writes it into Register 3. Functional Unit is basically just memory routers leading to a manifold and permitted to accumulate.

Subtract(Register 1, Register 2, Register 3)

Is a 4 word long instruction that destructively reads data from Register 1 and 2 and adds them, then sends them to a functional unit for addition and writes it into Register. Always outputs the difference of the greater number and the lesser number to prevent negatives. Functional Unit consists 3 of each input placed into a 1:1 gas mixer outputting to waste then outputting whatever is left of the inputs.

Compare(Register 1, Register 2, Boolean Register)

Is a 4 word long instruction that destructively reads data from both registers. Outputs True into the Boolean Register if Register 1 is greater than Register 2, outputs False otherwise.

Jump(variable length RAM address)

Is a variable length instruction that sets the Instruction Counter to the RAM address contained within.

Conditional Jump (Boolean Register, variable length RAM address)

Is a variable length instruction that tests the boolean inside the designated Boolean Register then sets the Instruction Counter to the RAM address contained within. If the Boolean Registers tests as false, increments the instruction counter. Given that it can only address the first tenth of the addressable instruction tape if you're using a 3 digit RAM system, it is recommended to have this jump to an adress that contains a Jump instruction to the actual address that you want to use. Increasing the decoder width by 1 solves this problem, unless you start using 4 digits of RAM space.

Memory Architecture

A memory is a single entry consisting of where a 32-bit floating point value is stored using the mole count of the . When stored or in transit, not a single mole or fraction thereof may be lost. This memory must be capable of fitting in any pipe configuration regardless of size and must have a pressure below when stored in a 70L pipenet container. While this limits the actual storable range of data, this limit is required to ensure that pumps can still pump and passive gates can still function.

Discussed below are the different memory storage architectures used for this ISA. Implementations will require the presence of all, with different sizes of each type depending on use case and desired performance.

Registers

Fast access no bullshit registers for storing single entries. Given special memory addresses for easy use and access. Functional units may have their own registers given how small and easy they are to use.

Cache

Given the tedium of constructing Random Access Memory, Cache will take the form of stack memory with a First-In-Last-Out architecture, stack heights depending on implementation. Note that lower stack heights have lower latency, thus different implementations may permit different stack heights for better performance. It is recommended that a cache hierarchy be established to allow for maximum functionality.

Random Access Memory

RAM, like all memory, has a very large area footprint and will require very long construction times. As such, it is reserved only for when necessary, such as the instruction tape. RAM consists of standard storage of canisters and is addressable using a decimal system. An address consists of n digits with n separate stages, each digit being represented using the GNS. Reading an address consists of taking the first digit and pushing it through a digit reader. Each digit output is linked to a signal gas transposer that is gated to the second digit, routing the gas of the second digit into another signal reader and so on until the last digit is read and signal gas reaches the destination. As such, adress space is 10^n for n digits. Note that an address space of 10^n requires a total of 10^(n-1)+10^(n-1) + 10^(n-2) ..... +10^(1) + 10^(0) digit readers to address assuming the entire address space is actually adressable. As such, it is advisable that one cut down on RAM sizes unless one likes building large amounts of it.

The instruction tape is Random Access Memory to allow for instruction blocks and jumps. Random Access Memory will be expanded as needed, but will be denoted using 3 decimals at most depending on implementation using the standard numbering system. 2 decimals will be sufficient for storing a tape 100 instructions long and as such will be the preferred size until such a time that more is required.

Constructing RAM is repetitive and tedious, while it is possible to add regular memory storage functionality to RAM, there are few use cases that warrant the time expenditure and area footprint required. Instead, become a better programmer and use stacks.

Clock Generator

Still up for a lot of debate and work, but planning on a 16-phase clock generator. First 4 cycles will be dedicated to LOAD operations, then 8 cycles for compute operations, then the last 4 for STORE operations. Maybe 4 more in the beginning for instruction decode operations? Might want to try separate instruction decoders and compute units with separate clocks and implement cycle hooks to allow for asynchronous compute.

Instruction Decoder

4-long instruction decoders are pretty limited, but will work for this very small ISA. Longer decoders are possible for adressing larger memory spaces, but really who needs more than a thousand spaces in RAM?

General Purpose Functional Units

These are generally used in other larger composite Functional Units.

AND gate - Just a default gas mixer with pressure maxed. Needs both sides filled to output and is thus an AND gate.

Digit Reader - Functional unit that takes an input of gas and passes it through a large number of comparators that read what type of gas it is according to the GNS. Each separate digit output can then be linked to another functional unit for logic purposes.

Parity Transposer - Reads an input gas of any type, then outputs a gas of a different specific type to A while routing the input gas to B. Attempting to read an input gas of the same type as the specific output type will result in double the input gas routed to B and no outputs to A.